/**
 * @file		dd_pmc_crg.h
 * @brief		PMC CRG11 driver
 * @note		None
 * @attention	None
 * 
 * <B><I>Copyright 2016 Socionext Inc.</I></B>
 */

/** @weakgroup dd_pmc_crg_overview
@{
	CM0 PMC - CRG11 Driver.<br>
	<br>
	Controls the clock frequency and clock-gating circuitry. <br>
	Creates internal resets by external factors or controlling register.
@}*//* --- end of dd_pmc_crg_overview */

#ifndef _DD_PMC_CRG_H_
#define _DD_PMC_CRG_H_

/** @weakgroup dd_pmc_crg_definition
@{*/

#include "driver_common.h"
#include "pmc.h"
#include "dd_arm.h"

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/* Definition															*/
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/* Enumeration															*/
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/* Structure															*/
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/* Global Data															*/
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/* Macro																*/
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// CRPLC
#define	Dd_PMC_CRG11_Get_CRPLC_PLLBYPASS()		(IO_PMC.CRG11.CRPLC.bit.PLLBYPASS)												/**< Get enter / exit PLL bypass mode Select */
#define	Dd_PMC_CRG11_Set_CRPLC_PLLBYPASS(val)	{INT32 s=Dd_ARM_DI();IO_PMC.CRG11.CRPLC.bit.PLLBYPASS=val;Dd_ARM_EI(s);}		/**< Set enter / exit PLL bypass mode Select */

// CRSTP
#define	Dd_PMC_CRG11_Get_CRSTP_STOPEN()			(IO_PMC.CRG11.CRSTP.bit.STOPEN)													/**< Get monitor of Stop mode Select */
#define	Dd_PMC_CRG11_Set_CRSTP_STOPEN(val)		{INT32 s=Dd_ARM_DI();IO_PMC.CRG11.CRSTP.bit.STOPEN=val;Dd_ARM_EI(s);}			/**< Set monitor of Stop mode Select */
#define	Dd_PMC_CRG11_Get_CRSTP_STOPMNT()		(IO_PMC.CRG11.CRSTP.bit.STOPMNT)												/**< Get enters stop mode Select */
#define	Dd_PMC_CRG11_Set_CRSTP_STOPMNT(val)		{INT32 s=Dd_ARM_DI();IO_PMC.CRG11.CRSTP.bit.STOPMNT=val;Dd_ARM_EI(s);}			/**< Set enters stop mode Select */

// CRRSC
#define	Dd_PMC_CRG11_Get_CRRSC_ARSTMODE()		(IO_PMC.CRG11.CRRSC.bit.ARSTMODE)												/**< Get pulse width of ARESETn Select */
#define	Dd_PMC_CRG11_Set_CRRSC_ARSTMODE(val)	{INT32 s=Dd_ARM_DI();IO_PMC.CRG11.CRRSC.bit.ARSTMODE=val;Dd_ARM_EI(s);}			/**< Set pulse width of ARESETn Select */
#define	Dd_PMC_CRG11_Get_CRRSC_SWRSTM()			(IO_PMC.CRG11.CRRSC.bit.SWRSTM)													/**< Get Software reset occurs immediately after SWRSTREQ Select */
#define	Dd_PMC_CRG11_Set_CRRSC_SWRSTM(val)		{INT32 s=Dd_ARM_DI();IO_PMC.CRG11.CRRSC.bit.SWRSTM=val;Dd_ARM_EI(s);}			/**< Set Software reset occurs immediately after SWRSTREQ Select */
#define	Dd_PMC_CRG11_Get_CRRSC_WDRSTM()			(IO_PMC.CRG11.CRRSC.bit.WDRSTM)													/**< Get Software reset occurs immediately after WDRSTREQ Select */
#define	Dd_PMC_CRG11_Set_CRRSC_WDRSTM(val)		{INT32 s=Dd_ARM_DI();IO_PMC.CRG11.CRRSC.bit.WDRSTM=val;Dd_ARM_EI(s);}			/**< Set Software reset occurs immediately after WDRSTREQ Select */

// CRSWR
#define	Dd_PMC_CRG11_Get_CRSWRS_SWRSTREQ()		(IO_PMC.CRG11.CRSWR.bit.SWRSTREQ)												/**< Get Software Reset */
#define	Dd_PMC_CRG11_Reset_CSWRS_SWRSTREQ()		{IO_PMC.CRG11.CRSWR.bit.SWRSTREQ = 0x00000001;}									/**< Set Software Reset */

// CRRSM(Reset and monitor register)
#define	Dd_PMC_CRG11_Get_CRRSM_WDRST()			(IO_PMC.CRG11.CRRSM.bit.WDRST)													/**< Get Watchdog Reset Monitor */
#define	Dd_PMC_CRG11_Clear_CRRSM_WDRST()		{INT32 s=Dd_ARM_DI();IO_PMC.CRG11.CRRSM.word = 0x0000000E;Dd_ARM_EI(s);}		/**< Set Watchdog Reset Clear */
#define	Dd_PMC_CRG11_Get_CRRSM_SWRST()			(IO_PMC.CRG11.CRRSM.bit.SWRST)													/**< Get SRREQ Bit Reset Monitor */
#define	Dd_PMC_CRG11_Clear_CRRSM_SWRST()		{INT32 s=Dd_ARM_DI();IO_PMC.CRG11.CRRSM.word = 0x0000000D;Dd_ARM_EI(s);}		/**< Set SRREQ Bit Reset Clear */
#define	Dd_PMC_CRG11_Get_CRRSM_PORST()			(IO_PMC.CRG11.CRRSM.bit.PORESET)												/**< Get RSTX Terminal Reset Monitor */
#define	Dd_PMC_CRG11_Clear_CRRSM_PORST()		{INT32 s=Dd_ARM_DI();IO_PMC.CRG11.CRRSM.word = 0x00000007;Dd_ARM_EI(s);}		/**< Set RSTX Terminal Reset Clear */

// CRCDC
#define	Dd_PMC_CRG11_Get_CRCDC_DCHREQ()			(IO_PMC.CRG11.CRCDC.bit.DCHREQ)													/**< Get clock divider mode Select */
#define	Dd_PMC_CRG11_Set_CRCDC_DCHREQ(val)		(IO_PMC.CRG11.CRCDC.bit.DCHREQ=val)												/**< Set clock divider mode Select */

// CRDM0
#define	Dd_PMC_CRG11_Get_CRDM0_DIVMODE()		(IO_PMC.CRG11.CRDM0.bit.DIVMODE)												/**< Get CLKx domain divider modes Select */
#define	Dd_PMC_CRG11_Set_CRDM0_DIVMODE(val)		(IO_PMC.CRG11.CRDM0.bit.DIVMODE=val)											/**< Set CLKx domain divider modes Select */

// CRLP0
#define	Dd_PMC_CRG11_Get_CRLP0_CSYSREQ_R()		(IO_PMC.CRG11.CRLP0.bit.CSYSREQ_R)												/**< Get clock gates of CLKx Select */
#define	Dd_PMC_CRG11_Set_CRLP0_CSYSREQ_R(val)	{INT32 s=Dd_ARM_DI();IO_PMC.CRG11.CRLP0.bit.CSYSREQ_R=val;Dd_ARM_EI(s);}		/**< Set clock gates of CLKx Select */
#define	Dd_PMC_CRG11_Get_CRLP0_CEN()			(IO_PMC.CRG11.CRLP0.bit.CEN)													/**< Get monitor internal CENx signals Select */

// CRDM1
#define	Dd_PMC_CRG11_Get_CRDM1_DIVMODE()		(IO_PMC.CRG11.CRDM1.bit.DIVMODE)												/**< Get CLKx domain divider modes Select */
#define	Dd_PMC_CRG11_Set_CRDM1_DIVMODE(val)		(IO_PMC.CRG11.CRDM1.bit.DIVMODE=val)											/**< Set CLKx domain divider modes Select */

// CRLP1
#define	Dd_PMC_CRG11_Get_CRLP1_CSYSREQ_R()		(IO_PMC.CRG11.CRLP1.bit.CSYSREQ_R)												/**< Get clock gates of CLKx Select */
#define	Dd_PMC_CRG11_Set_CRLP1_CSYSREQ_R(val)	{INT32 s=Dd_ARM_DI();IO_PMC.CRG11.CRLP1.bit.CSYSREQ_R=val;Dd_ARM_EI(s);}		/**< Set clock gates of CLKx Select */
#define	Dd_PMC_CRG11_Get_CRLP1_CEN()			(IO_PMC.CRG11.CRLP1.bit.CEN)													/**< Get monitor internal CENx signals Select */

// CRDM3
#define	Dd_PMC_CRG11_Get_CRDM3_DIVMODE()		(IO_PMC.CRG11.CRDM3.bit.DIVMODE)												/**< Get CLKx domain divider modes Select */
#define	Dd_PMC_CRG11_Set_CRDM3_DIVMODE(val)		(IO_PMC.CRG11.CRDM3.bit.DIVMODE=val)											/**< Set CLKx domain divider modes Select */

// CRLP3
#define	Dd_PMC_CRG11_Get_CRLP3_CSYSREQ_R()		(IO_PMC.CRG11.CRLP3.bit.CSYSREQ_R)												/**< Get clock gates of CLKx Select */
#define	Dd_PMC_CRG11_Set_CRLP3_CSYSREQ_R(val)	{INT32 s=Dd_ARM_DI();IO_PMC.CRG11.CRLP3.bit.CSYSREQ_R=val;Dd_ARM_EI(s);}		/**< Set clock gates of CLKx Select */
#define	Dd_PMC_CRG11_Get_CRLP3_CEN()			(IO_PMC.CRG11.CRLP3.bit.CEN)													/**< Get monitor internal CENx signals Select */

// CRDM4
#define	Dd_PMC_CRG11_Get_CRDM4_DIVMODE()		(IO_PMC.CRG11.CRDM4.bit.DIVMODE)												/**< Get CLKx domain divider modes Select */
#define	Dd_PMC_CRG11_Set_CRDM4_DIVMODE(val)		(IO_PMC.CRG11.CRDM4.bit.DIVMODE=val)											/**< Set CLKx domain divider modes Select */

// CRLP4
#define	Dd_PMC_CRG11_Get_CRLP4_CSYSREQ_R()		(IO_PMC.CRG11.CRLP4.bit.CSYSREQ_R)												/**< Get clock gates of CLKx Select */
#define	Dd_PMC_CRG11_Set_CRLP4_CSYSREQ_R(val)	{INT32 s=Dd_ARM_DI();IO_PMC.CRG11.CRLP4.bit.CSYSREQ_R=val;Dd_ARM_EI(s);}		/**< Set clock gates of CLKx Select */
#define	Dd_PMC_CRG11_Get_CRLP4_CEN()			(IO_PMC.CRG11.CRLP4.bit.CEN)													/**< Get monitor internal CENx signals Select */

// CRDM5
#define	Dd_PMC_CRG11_Get_CRDM5_DIVMODE()		(IO_PMC.CRG11.CRDM5.bit.DIVMODE)												/**< Get CLKx domain divider modes Select */
#define	Dd_PMC_CRG11_Set_CRDM5_DIVMODE(val)		(IO_PMC.CRG11.CRDM5.bit.DIVMODE=val)											/**< Set CLKx domain divider modes Select */

// CRLP5
#define	Dd_PMC_CRG11_Get_CRLP5_CSYSREQ_R()		(IO_PMC.CRG11.CRLP5.bit.CSYSREQ_R)												/**< Get clock gates of CLKx Select */
#define	Dd_PMC_CRG11_Set_CRLP5_CSYSREQ_R(val)	{INT32 s=Dd_ARM_DI();IO_PMC.CRG11.CRLP5.bit.CSYSREQ_R=val;Dd_ARM_EI(s);}		/**< Set clock gates of CLKx Select */
#define	Dd_PMC_CRG11_Get_CRLP5_CEN()			(IO_PMC.CRG11.CRLP5.bit.CEN)													/**< Get monitor internal CENx signals Select */

/* @} */	// dd_pmc_crg_definition group

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/* Nothing Special */

#endif	// _DD_PMC_CRG_H_
